Written Test
Profile : Digital Design Engineer
Pattern : Completely Subjective. Application level
questions.
1. Given a buffer. When an input pulse of 100Mhz with
50% duty cycle is applied, the output is having a duty cycle of 60%. What is
the output duty cycle if the input frequency is 50Mhz. [ assume delay of
bnuffer is independent of freq ]
2. Given a fifo. The read ptr and write ptr logic
gives two signals at the output fifo full and fifo half-full as shown in the
figure.
Generate circuit A using synchronous sequential circuitry.
3. Given a program with 4 instructions. First itsw
passed through a system with 3 stage pipeline and working frequency of 100Mhz.
Now the system is modified to a 6 stage pipeline with 150Mhz frequency. What is
the improvement achieved because of this modification?
4. Design system 2, such that OUT = IN1
5. Given
Tclk_q = 1ns
Tsetup = 1ns
T(inv) = 1ns
T(buff) = 1ns
T(D_Q) = 1ns
(A)
Find the maximum frequency of operation’
(B)
If hold time = 1ns, will there be any hold
violations?
(C)
How will jitter affect the frequeny of operation
and the hold condition, if the jitter = +- 0.5ns
6. There are 2 bags. First bag contains 3 white and
1 black ball. Second bag contains 1 white and 3 black balls. 1 bag is selected
at random. From the randomly selected bag a person selects a ball and finds
that it is black. He then replaces it and selects another ball. What is the
probability that it is also black?
7. Given
Find the waveform at y.
8.
One simple question based on combinational
circuits.
9.
Find the voltage at y
10.
A memory of 16MBits is given.
Short = 16bits
Word = 32 bits
Normal = 64bits
Represent the memory using address
map so that right/left shift gives word and normal locations.
11.
Given a DFF. Clk frequency = 100Mhz. Data
frequency = 5Mhz. Tsetup = 100ps.
(A)
What is the rate of metastability/sec ?
(B)
If you cannot remove the Tsetup from fabrication
point of view, how can you remove the metastability issue?
(C)
How much should be the Tsetup so that there will
be only 1 violation in 10 years?
12.
S1 closed
at T0, and opened at T1.
S2 closed at T2.
T0<T1<T2
Find V_120f af T2 (after settling).
Interview
I was personally "lucky", (lucky so that i can write this piece now), enough to attend the interviews of Qualcomm, Intel, Synopsys and Analog Devices. And I will rate ADI interview as the toughest among all these.
There were 2 rounds of interviews, each extending to 1 hour.
In the first round they stick to the question paper they set and concentrated on the questions where we made mistake. Also, more practical aspect of the questions were touched upon, instead of the ready made theoretical questions.
In the second round they concentrated on the resume and basic digital vlsi circuits.
