In this post, i just want to talk about the most preferred topic by the interviewers in the recent past. I have also given the best resources available to learn them.

1. Static timing analysis

Study this in detail.

Learn to solve problems involing setup time and hold time. [stick to basic problems]
Especially understand the term "jitter".
Follow VLSI-EXPERT







2. Low Power VLSI Design

One of the main topic for Intel and Qualcomm interviews.
Follow: NPTEL COURSE BY PROF. AJIT PAL from IIT Kharagpur


3. Computer Architecture Basics

Again a topic important for Intel and Nvidia.
The most important point here is learn computer architecture with a vlsi view point. Learn the system architecture and the designing concepts. Not the instruction set architecture.
Follow: IIT Delhi - Follow this from 11th lecture

4. Verilog

Must for a digital designer.
Follow: Samir Palnitkar

5. Miscellaneous

FIFO problems, Divide by circuits.


If you have some prior knowledge about any scripting languages, it is an added advantage.

Fundamentals 
NOTE: these notes can be used as refresher notes only. Very concisely written.
 
Need for Low Power Circuit Design 
1. Lower nodes like 10nm
2. Greater importance by the advent of portable battery driven devices like laptops, cell phones,PDAs etc


Sources of Power Dissipation
1. Dynamic :
         A. Switching Power Dissipation : Due to charging and discharging of capacitors
         B. Short Circuit Power Dissipation : When both upper PMOS section and lower NMOS section are both in saturation and thereby allow a direct path from vdd to gnd, there will be high dissipation in power.
         C. Glitching Power Dissipation : Due to unbalanced circuit networks. (google it)

2. Static :
         A. Leakage Power Dissipation

note:
See the derivations for each of the powers.
See on what factors each of these depend
See how to mitigate the effects

Short Channel Effects 
As the device geometry reduces, the potential distribution in channel starts to depend both on the Ex [controlled by gate bias] and Ey[controlled by drain voltage]. ie, potential distribution becomes 2D.
Earlier it was 1D- since the approx. Ex>>Ey was valid.

1. Mobility degredation

Lateral Field Effect: In case of short channels, as the lateral field is increased, the channel mobility becomes field-dependent and eventually velocity saturation occurs (which was referred to in the previous lecture). This results in current saturation.

Vertical Field Effect: As the vertical electric field also increases on shrinking the channel lengths, it results in scattering of carriers near the surface. Hence the surface mobility reduces.

2. Sub-threshold current

3. Vth variation
4. Drain Induced Barrier Lowering and Punch Through
5. Surface Scattering
6. Velocity Saturation
7. Hot Electron Effect.

Low-Power Design Approaches
Low-Power Design through Voltage Scaling :
1. VTCMOS circuits
2. MTCMOS circuits

Architectural Level Approach:

Pipelining Approaches.

Switched Capacitance Minimization Approaches:
System Level Measures
Circuit Level Measures
Mask level Measures

Specific Points
1. How cascading of inverters reduces the overall delay? optimum size problem.
2. Prove that a NAND gate is better than NOR gate as universal gate.
    ans : in terms of area, delay and noise margin
3. Dynamic Logic Circuits
    A. Domino Logic
    B. NoRA Logic
4. Theory behind CHARGE LEAKAGE, CHARGE SHARING AND CLOCK SKEW problems.
     Find out reasons and solutions.
5. Leakage Power reduction techniques
    A. Standby power
         -transistor stacking
         -VTCMOS
         -MTCMOS
         -power gating
    B. Run time power reduction
         -Dual vth circuits
         -Dynamic vdd scaling
         -Dynamic vth scaling[vth hopping]

Low-Voltage Low-Power Adders
Standard Adder Cells, CMOS Adder’s Architectures – Ripple Carry Adders, Carry LookAhead Adders, Carry Select Adders, Carry Save Adders, Low-Voltage Low-Power Design Techniques –Trends of Technology and Power Supply Voltage, Low-Voltage Low-Power Logic Styles.

Low-Voltage Low-Power Multipliers
Types of Multiplier Architectures, Braun Multiplier, BaughWooley Multiplier, Booth Multiplier, Introduction to Wallace Tree Multiplier.

Low-Voltage Low-Power Memories
Basics of ROM, Low-Power ROM Technology, Future Trend and Development of ROMs, Basics of SRAM, Memory Cell, Precharge and Equalization Circuit, Low-Power SRAM Technologies, Basics of DRAM, Self-Refresh Circuit, Future Trend and Development of DRAM

1. Sequential block with blocking assignments
The statements in a sequential block are processed in the order they are specified. A statement is executed only after its preceding statement completes execution. If delay or event control is specified, it is relative to the simulation time when the previous statement in the block completed execution.


2. Sequential block with non-blocking assignments
If no regular delays are specified then the right-hand expressions of all non-blocking statements are evaluated then the assignments are performed according to intra-assignment delays. If regular delay controls are specified then the execution order of non-blocking assignments is defined by regular delay controls.


3. Parallel block with blocking assignments
In case of parallel blocks all the statements start to execute at time 0. However the 
sequence of statements is still being taken into account. That is the variables used in each succeeding statement take the values assigned to them in preceding statements.

4. Parallel block with non-blocking assignments
In this case all the statements start to execute at time 0 and the right-hand expressions of all statements are evaluated immediately provided that there are no regular delays. It means that the variables used in each succeeding statement does not take the values assigned to them in preceding statements.

So summarizing all these cases one can say that by blocking/non-blocking statements it is controlled whether the values of variables assigned to them in preceding statements are used in succeeding statements or not. And by the Sequential/Parallel blocks it is controlled whether the simulation time is relative to the time when previous statement completed it's execution or to the time when the 
block was entered.


thanks to : http://www.edaboard.com/thread103924.html