Source Delay or Source Latency It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design". Delay from clock source to beginning of clock tree (i.e. clock definition point). The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point...
Integrated Clock Gating Cells Clock gating is a common technique for reducing clock power by shutting off the clock to modules by a clock enable signal. Clock gating functionally requires only an AND or OR gate. Consider you were using an AND gate with the clock. The high EN edge may come anytime and may not coincide with a clock edge. In that...
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In this post, i just want to talk about the most preferred topic by the interviewers in the recent past. I have also given the best resources available to learn them. 1. Static timing analysis Study this in detail. Learn to solve problems involing setup time and hold time. [stick to basic problems] Especially understand the term "jitter". Follow VLSI-EXPERT 2. Low Power VLSI...
