Fundamentals 
NOTE: these notes can be used as refresher notes only. Very concisely written.
 
Need for Low Power Circuit Design 
1. Lower nodes like 10nm
2. Greater importance by the advent of portable battery driven devices like laptops, cell phones,PDAs etc


Sources of Power Dissipation
1. Dynamic :
         A. Switching Power Dissipation : Due to charging and discharging of capacitors
         B. Short Circuit Power Dissipation : When both upper PMOS section and lower NMOS section are both in saturation and thereby allow a direct path from vdd to gnd, there will be high dissipation in power.
         C. Glitching Power Dissipation : Due to unbalanced circuit networks. (google it)

2. Static :
         A. Leakage Power Dissipation

note:
See the derivations for each of the powers.
See on what factors each of these depend
See how to mitigate the effects

Short Channel Effects 
As the device geometry reduces, the potential distribution in channel starts to depend both on the Ex [controlled by gate bias] and Ey[controlled by drain voltage]. ie, potential distribution becomes 2D.
Earlier it was 1D- since the approx. Ex>>Ey was valid.

1. Mobility degredation

Lateral Field Effect: In case of short channels, as the lateral field is increased, the channel mobility becomes field-dependent and eventually velocity saturation occurs (which was referred to in the previous lecture). This results in current saturation.

Vertical Field Effect: As the vertical electric field also increases on shrinking the channel lengths, it results in scattering of carriers near the surface. Hence the surface mobility reduces.

2. Sub-threshold current

3. Vth variation
4. Drain Induced Barrier Lowering and Punch Through
5. Surface Scattering
6. Velocity Saturation
7. Hot Electron Effect.

Low-Power Design Approaches
Low-Power Design through Voltage Scaling :
1. VTCMOS circuits
2. MTCMOS circuits

Architectural Level Approach:

Pipelining Approaches.

Switched Capacitance Minimization Approaches:
System Level Measures
Circuit Level Measures
Mask level Measures

Specific Points
1. How cascading of inverters reduces the overall delay? optimum size problem.
2. Prove that a NAND gate is better than NOR gate as universal gate.
    ans : in terms of area, delay and noise margin
3. Dynamic Logic Circuits
    A. Domino Logic
    B. NoRA Logic
4. Theory behind CHARGE LEAKAGE, CHARGE SHARING AND CLOCK SKEW problems.
     Find out reasons and solutions.
5. Leakage Power reduction techniques
    A. Standby power
         -transistor stacking
         -VTCMOS
         -MTCMOS
         -power gating
    B. Run time power reduction
         -Dual vth circuits
         -Dynamic vdd scaling
         -Dynamic vth scaling[vth hopping]

Low-Voltage Low-Power Adders
Standard Adder Cells, CMOS Adder’s Architectures – Ripple Carry Adders, Carry LookAhead Adders, Carry Select Adders, Carry Save Adders, Low-Voltage Low-Power Design Techniques –Trends of Technology and Power Supply Voltage, Low-Voltage Low-Power Logic Styles.

Low-Voltage Low-Power Multipliers
Types of Multiplier Architectures, Braun Multiplier, BaughWooley Multiplier, Booth Multiplier, Introduction to Wallace Tree Multiplier.

Low-Voltage Low-Power Memories
Basics of ROM, Low-Power ROM Technology, Future Trend and Development of ROMs, Basics of SRAM, Memory Cell, Precharge and Equalization Circuit, Low-Power SRAM Technologies, Basics of DRAM, Self-Refresh Circuit, Future Trend and Development of DRAM