Logic Simulation, Synthesis of RTL and Import to cadence
2:22:00 PM
Synopsys unix set up : http://www.vtvt.ece.vt.edu/vlsidesign/tutorialSynopsys_unixSetup.php
Perform logic simulation : using any of the tools like ISE, vivado, modelsim : http://www.vtvt.ece.vt.edu/vlsidesign/tutorialSynopsys_logicSym.php
Use Design Vision of Synopsys for logic synthesis : http://www.vtvt.ece.vt.edu/vlsidesign/tutorialSynopsys_logicSynth.php
Import the synthesized design into cadence composer schematic view : http://www.vtvt.ece.vt.edu/vlsidesign/tutorialCadence_importVerilog.php
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